1. Technical Field
The present invention relates to large scale data processing systems and, more specifically, to error servicing circuitry and control logic in a data processing machine.
2. Summary of Prior Art
In present day data processing systems, including high speed digital computers, a plurality of resources or functional units are provided to perform various functions. The functional units which generally comprise a data processing system are known in the art and are described in the overview presented with reference to FIG. 2. Approximately 1/3 of the hardware in such a system is dedicated to error detection and processing and is transparent to a user.
Data processing system design efforts have focused on increasing processing speed and the density of components. These efforts have been generally successful and emphasis in the industry is shifting towards accuracy and overcoming limitations induced by pin connections. With respect to accuracy, emphasis has been placed on the ability to not only detect and scan out an error, but also to scan-in or "force" an error. One well known scan out and scan-in procedure has been developed by Fujitsu Corporation and is referred to as Fujitsu scan.
Referring to FIG. 1, a scannable latch, generally according to Fujitsu scan, which includes functional and scan implementing components is shown. The specific combination of gates within the block indicated by dashed line 11 illustrates the functional latch component. The scan-in and scan out operations are provided by an addressable scan-in gate 12 and an addressable scan out gate 13, respectively. Other inputs to the functional latch 11 are a system clock, a data input and a clear. The functional latch 11 may be located in any of the functional units and at any location where a latch is so desired.
In order to test error servicing hardware, it is possible to force a certain logic state in the functional latch 11, which for a particular known condition would represent an error state. Error servicing logic then makes a determination as to whether an error detection device in communication with the functional latch 11 under test has generated an error signal in response to the error input by gate 12.
The functioning of scan-in gate 12 and scan out gate 13 are generally known in the art. Essentially, the scan-in gate 12 has two inputs: an error data signal and an address. The addressing scheme may utilize a three-dimensional matrix in which one dimension "z" is used to indicate a particular functional unit and the remaining two dimensions (x, y) create a matrix which is used to designate a particular location on a chip on the board containing the selected functional unit. Scan out gate 13 also has two inputs. The first is the output of functional gate 11 and the second is an address (the same as for scan-in gate 12). The output of functional latch 11 can, therefore, be scanned out by the application of an address for latch 11 at scan out gate 13.
In Fujitsu scan, the error data input is a scan clock signal which is a square wave having an active period, for example, of approximately 10 system clock cycles. A transient fault is simulated by addressing the desired latch and permitting the scan clock to be input to the scan-in input which is effectively the latch reset. This causes the latch to be reset at least every other 10 system clock cycles, the 10 cycle active period of the scanning clock simulating a transient error.
A significant limitation of the Fujitsu scan technique, however, is that it fails to permit a forcing of stuck-at faults, those faults which have an indefinite duration. A further disadvantageous limitation of the Fujitsu scan is that it is only applied to latches, and though latches represent an important part of testable circuitry, there are other portions of a data processing system that warrant testing, such as combinational logic, signal lines and other sequential logic. The Fujitsu scan does not provide these functions. Furthermore, due to the dense packaging of integrated circuits, there may not be sufficient die area to implement scan-in and scan out schemes for each of these additional scan points. Thus, there is a need to provide scannable access to locations other than latches and in a minimally intrusive manner that does not adversely compromise a high density of functional components.